1. Field of the Invention
The invention relates to testing of electronic devices. In particular, the invention relates to monitoring a net in a device to determine if the net is the source of a failure.
2. Description of the Related Art
Chip complexity and increased packaging used in electronic devices are decreasing device geometries at a rapid pace. Currently, geometries in electronic devices have migrated from 0.18 xcexcm down to 0.13 xcexcm. The trend to smaller device geometries is expected to continue in the future. As device geometries decrease, problems associated with testing and debugging devices continue to become more difficult.
To help obviate some of the difficulties of testing these small geometries, designers are making extensive use of simulation and design verification software to eliminate design problems before a device is fabricated. While simulation and verification software do identify some design problems before fabrication, many designs do not yield fully operational, full specification, parts without first undergoing lengthy, and expensive, debug phases. In addition, even if all the design problems are identified and corrected prior to fabrication, defects may be introduced into the device during the manufacturing process.
During the test and debug process, probing of internal nets of a device is becoming an increasingly valuable tool. Probing internal nets of a device assists in identifying and isolating portions internal to a device that are not performing properly. One technique used to provide access to internal nets is to include pads on some xe2x80x9ccriticalxe2x80x9d internal nets during the design of a device, and thereby allow access to these nets during test and debug. However, the vast majority of internal nets will not have pads, and therefore no direct access to these nets is possible.
Packaging density and chip complexity restrict a device designer in placement of pads on internal nets due to space limitations within the device. This is particularly true in very large scale integrated circuits (VLSI) such as gate arrays, field programmable gate arrays (FPGA), and application specific integrated circuits (ASIC) such as mixed signal integrated circuits. The lack of direct access to all of the internal nets of a device complicates the test and debug process.
Certain aspects of device layout further increases the complexity of testing and debugging. For example, it is very difficult to detect a defect, such as a manufacturing defect, at the bottom of a trench or a via. Typically, detection of a defect at the bottom of a trench or via requires a failure analysis of the device using instrumentation such as electron microscopes. In addition, intermittent failures, such as stress related intermittent failures, are especially difficult to locate due to their nonrepetitive nature.
Several techniques have evolved in testing and debugging electronic devices. Some of these techniques include functional testing, burn-in testing, and defect detection.
Functional testing is typically used to verify proper operation of an electronic device. For example, an IC may undergo functional testing following the completion of the IC fabrication process. Test leads, or probes, are connected to the Input and Output (I/O) pins of the IC. Test stimuli are applied to input pins of the IC and the output pins of the IC are monitored to determine if expected signals are produced. Functional testing is typically performed under normal ambient conditions, so that the device under test is not being exposed to any type of external stress, for example, environmental stress such as elevated temperature.
Another technique used in testing and debugging electronic devices is burn-in testing. Typically, a burn-in test of a device involves elevating the ambient temperature of a device that has power applied. A burn-in test will stress the entire device, including all nets within the device. Due to the environment that the device is being tested in, it may not be practical to decapsulate a device to expose the internal nets of the device due to environmental concerns, such as, condensation in the device. Furthermore, even if the device could be decapsulated, making the internal nets of the device accessible, failure of an individual net may be difficult to identify through burn-in testing because the entire device and all nets are stressed equally.
A third technique, defect detection, monitors the device I/O pins as well as probes internal nets of the device. Typically, probing internal nets of a device requires that the device be decapsulated, thereby providing access to the internal nets. Because the device is decapsulated, environmental stressing of the decapsulated device may be impractical.
One technique used to probe internal nets uses mechanical probes. Mechanical probes may be aligned, and physically contact an internal net of the device. One drawback to using mechanical probes is that they may load the electrical circuit of a net being tested. For example, the mechanical probes may increase circuit capacitance and therefore distort the measured performance of the circuit from how the circuit would perform without the added loading of the mechanical probes.
A technique that has been developed to eliminate loading of a circuit of a device under test is an electronic-beam (e-beam) probe. Recent development of e-beam probe tools and techniques have greatly assisted in overcoming some of the problems involved in probing internal nodes of electronic devices for debug and other purposes.
E-beam probing uses the principle of voltage contrast in a scanning electron microscope (SEM). A conventional SEM image is produced by raster-scanning a finely-focused beam of primary electrons over a device under test as signals are applied to the device. Secondary electrons are produced as the primary beam is reflected from the device under test. The secondary electrons reflected from the device are measured and, using a scintillator, photo-multiplier tube (PMT) and associated electronics, an image of the nets of the device under test is produced. The energy of the secondary electrons produced by the device under test results from variations in the electrical potential on the surface of conductors, or nets, within the device. Secondary electrons that strike the face of the scintillator produce a number of photons proportional to the energy of the secondary electrons, which are emitted from the scintillator and strike the face of the PMT. The PMT outputs a voltage proportional to the number of photons that strike its face. The voltage out of the PMT is amplified by associated electronics and used to produce an image that corresponds to the electrical potential on the surface of the conductors and nets within the device. In this way, the e-beam technique provides an indication of node voltages.
For example, positive voltages may appear as dark areas in the image, corresponding to a low secondary electron count. Zero, or negative, voltages may appear as light areas in the image, corresponding to a higher secondary electron count.
E-beam probing offers several advantages over other probing techniques, such as mechanical probing. An e-beam probe is typically passive, meaning that it does not interact or load the electrical circuit that is being monitored. In contrast, as mentioned above, mechanical probes may load the circuit being tested, making measurements inaccurate.
Therefore, there is a need for an effective way to monitor the operation of internal nets of an electronic device, without affecting the operation of the device, identifying particular nets that may be the source of failure.
Identifying a failure net in an integrated circuit (IC) whose output indicates an IC failure includes determining a potential failure net by observing a signal produced by the net that indicates failure, stressing the potential failure net while leaving other IC nets unaffected, and observing a change in the signal produced by the potential failure net in response to the stress, thereby identifying the potential failure net as a failure net of the IC.
Stressing a net in a device, or IC, may include aligning an external source of stress to the net, applying stress to the net while leaving other device nets unaffected, and monitoring the net, while the stress is being applied, to determine if the net fails while it is being stressed.
Locally stressing a net in a device, or IC, may include aligning an e-beam probe onto a suspect net within the device. Once the e-beam probe is aligned with the suspect net, the current in the e-beam is increased, thereby locally applying stress the device near the suspect net.
Other features and advantages of the present invention should be apparent from the following description of the preferred embodiment, which illustrates, by way of example, principles of the invention.